Advancements in miniaturization technology have brought about nanoscale and ultrafast semiconductor devices having a gate length of 30 nm or less.
In such a nanoscale and ultrafast transistor, areas of channel regions just below gate electrodes are significantly small compared to those in a conventional semiconductor device. Accordingly, the mobility of electrons or holes through the channel regions is largely affected by stress applied to the channel regions. Given this factor, many approaches have been developed that optimize the stress applied to the channel regions, thereby improving the operation speed of semiconductor devices.
One of conventionally proposed structures is directed to the improvement of the operation speed of an n-channel MOS transistor, and involves forming a stress film (a typical example of such is an SiN film) having a tensile stress in such a manner as to include the gate electrode in the element region of the n-channel MOS transistor. In this way, the electron mobility in the channel region just below the gate electrode is improved.
Another conventionally proposed structure is directed to the improvement of the operation speed of a p-channel MOS transistor, and involves forming a stress film (such as an SiN film) having a compressive stress in such a manner as to include the gate electrode in the element region of the p-channel MOS transistor. In this way, the hole mobility in the channel region just below the gate electrode is improved.
Furthermore, a proposed semiconductor integrated circuit device has a structure in which a stress-application n-channel MOS transistor and a stress-application p-channel MOS transistor are integrated.
Such a semiconductor integrated circuit device is formed by the following procedures, for example.
That is, after an n-channel MOS transistor and a p-channel MOS transistor are formed on a semiconductor substrate, the entire structure is, first, covered by a tensile stress film. Patterning is then applied to the structure so as to selectively remove the tensile stress film from a region in which the p-channel MOS transistor is formed.
Subsequently, a compressive stress film is formed on the resultant structure in such a manner as to directly cover the p-channel MOS transistor in the region where the p-channel MOS transistor is formed, but cover the n-channel MOS transistor with the tensile stress film interposed in between in a region where the n-channel MOS transistor is formed. Next, the compressive stress film is selectively removed from the region where the n-channel MOS transistor is formed.
Alternatively, the compressive stress film may be formed first, and the tensile stress film may be subsequently formed.
Patterning of the compressive stress film is performed in the region where the n-channel MOS transistor is formed, and on the other hand, patterning of the tensile stress film is performed in the region where the p-channel MOS transistor is formed. It is therefore considered advantageous to use, for the patterning in each element region, an ion implantation mask used at the time of the well formation since this eliminates the necessity of designing a new mask pattern.
In view of this, a method of manufacturing a semiconductor integrated circuit device proposed by Japanese Laid-Open Patent Publication No. 2006-173432 involves the following procedures. That is, in the patterning of the tensile stress film, a mask used for the well formation in the element region of the p-channel MOS transistor is employed so as to leave a resist pattern only in the element region of the n-channel MOS transistor and remove the tensile stress film from the remaining region. On the other hand, in the patterning of the compressive stress film, a mask used for the well formation in the element region of the n-channel MOS transistor is employed so as to expose only the element region of the n-channel MOS transistor and, then, remove the tensile stress film only from the element region of the n-channel MOS transistor while covering the remaining region with a resist pattern.
In a semiconductor integrated circuit device formed in the above-mentioned manner, the tensile stress film is formed only in the element region of the n-channel MOS transistor and the remaining element region is covered by the compressive stress film. Alternatively, the compressive stress film is formed only in the element region of the p-channel MOS transistor and the remaining element region may be covered by the tensile stress film.
On the other hand, the area occupancies of the n-channel MOS transistor and the p-channel MOS transistor on the semiconductor substrate vary from product to product. Therefore, in such semiconductor integrated circuit devices, the area ratio between the tensile stress film and the compressive stress film is generally different from product to product.
Etching conditions for patterning are different between the tensile stress film and the compressive stress film. Accordingly, in the case where the area ratio between the tensile stress film and the compressive stress film on the semiconductor substrate is different among products, the etching conditions for patterning the tensile stress film and the compressive stress film need to be adjusted for individual products. However, it is difficult to optimize the etching conditions with respect to each product.
Recently, a business has been adopted that leases out different regions out of the same semiconductor wafer to various customers and manufactures semiconductor integrated circuit devices having different specifications according to individual requests for trial production. The above-described conventional manufacturing method cannot deal with cases like this.